In reply to ben@SystemVerilog.us:
@cgales, This looks like some extra logic in interface.
The interface should have internal logic that will drive the wires from logic or tri-state them
This kind of logic we generally have in Driver component. Where if the Driver is not connected to testbench, same interface can be also used as slave.
@ben, your solution in given link looks good. But there also, declaring clocking variable as inout might be unnecessary.
Just replacing “logic” with “wire” in above code seem to have done the job!
interface intf(bit clock);
wire a; //logic a;
clocking drvCb @(posedge clock);
output a; //Can be driven through procedural block
endclocking
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