I was reading specs of protocol, and there is two different buses for wdata and rdata, but there is only one control signal to control the type of transfer like if PWRITE is high then WDADTA will be valid and if it’s low then RDATA will be valid during that cycle. so it will be more efficient to take only one bus for data transfer. then why we have to take two ?
You are asking a hardware / architecture question in a verification forum.
My guess would be that the turnaround time for a read followed by a write or a write-read is faster if there are separate buses. Switching between a initiator to a responder and back might take too much time vs. dedicated lines.
In reply to satyajeett:
I was reading specs of protocol, and there is two different buses for wdata and rdata, but there is only one control signal to control the type of transfer like if PWRITE is high then WDADTA will be valid and if it’s low then RDATA will be valid during that cycle. so it will be more efficient to take only one bus for data transfer. then why we have to take two ?
There is a different understanding with respect to bus in the APB Spec and the common bus understanding.
APB means 2 different data signals for read and write PRDATA and PWDATA. The spec mentions also an address bus which is PADDR, also a signal.
In reply to satyajeett:
A colleague suggested that one possible reason could be unlike read bus, write bus has PSTRB.
This enables to send sparse data transfer on the write data bus.
In reply to ABD_91:
Yes, there is need of strobe signal to send sparse data if any but it was introduced in apb 4 and WDATA and RDATA is taken separate from previous versions.