Why the tri state declared gpio glitch-free assertion triggers only once?

SystemVerilog
1

I’m trying to create a glitch free check on gpio pin, which declared as tri state in my tb_top, Even though there is variation in the GPIO_P[0] pin certainly below assertions triggers only once, I even tried with @(posedge tb_top.GPIO_P[0] or negedge tb_top.GPIO_P[0]) But no use.

property gpio_p_0; 
  realtime  time0;
  @(`tb_top.GPIO_P[0])
  (1,time0 = $realtime) |=> (($realtime - time0) >= 3ns)[*1:$];
endproperty : gpio_p_0

assert_gpio_p_0 : assert property (gpio_p_0) 
  uvm_report_info("GPIO_GLITCH_FREE_CHECK", $psprintf("PASSED: GPIO_GLITCH_FREE on GPIO[0] assertion successful!"));
else 
  `uvm_error("GPIO_0_GLITCH_FREE_ASSERT", $psprintf("\n\nFAILED: GPIO_GLITCH_FREE_CHECK gpio_p_0 Assertion failed!\n"))
2

In reply to balramnaik03:
You would need to delve in the LRM to determine what tri-state changes constitute an event.
In the meantime, consider those options:

  1. use $changed. @$changed(`tb_top.GPIO_P[0])
    ?? Is @$changed(sig) considered an event when sig transitions from X to 2, or from 1 to X?
    Is a change from x to 1 considered
    // **** $changed requires a clock, that would NOT work for what you want.
    //Updated by Ben
  2. use combinational support logic (with the always block) to test changes in values of (`tb_top.GPIO_P[0]) and then based on the the change in values, create your own event to be used by the assertion.

Ben Cohen
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2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.

3

In reply to ben@SystemVerilog.us:

Thanks Ben, 2nd approach is correct, But when i tried $changed with clk also not working, what is the wrong with below code.??

property gpio_p_0; 
  realtime  time0;
  @(posedge tb_top.clk)
  ($changed(`tb_top.GPIO_P[0]), time0 = $realtime) |=> (($realtime - time0) >= 3ns)[*0:$];
endproperty : gpio_p_0
4

In reply to balramnaik03:

  1. when using $changed(z)…
    Use the ss1 before it is to take care of the first cycle.
  2. Check in 1800 if transitions like x to 1/0, z to 1/0 are considered changes.
    You should could also run a small test to see how the simulator handles this.

In my language learning experiences with VHDL, Verilog and SV I ran small tests for things I didn’t understand. In most cases the simulation tools implemented that issue correctly, and that clarified my issues.

Ben systemverilog.us