In reply to ben@SystemVerilog.us:
Thanks Ben, 2nd approach is correct, But when i tried $changed with clk also not working, what is the wrong with below code.??
property gpio_p_0;
realtime time0;
@(posedge tb_top.clk)
($changed(`tb_top.GPIO_P[0]), time0 = $realtime) |=> (($realtime - time0) >= 3ns)[*0:$];
endproperty : gpio_p_0