Hi,
I am writing a new SV UVM testbench environment for my existing C++ and verilog based testbench. It is a very complex DUT and want to use a portion of existing C++ testbench code for generating a portion of vectors. Methodology we are following is not primarily constrained random… we are trying to come up with a graph based generation for input vectors
We are a team with minimum/no experience in Systemverilog
Main concern from team members is their skill in Sys verilog and want to use most of the C++ code to make life easy.
My primary questions:
In this case, does any have suggestions why we should to stick to a pure SV environment?
Are there any industry standards or examples or suggestions for writing a graph based verif environment (using complete SV)
(Right now, we are planning to have our own format to define how graphs should be directed and SV parser to direct testbench accordingly)
In my opinion UVM provides a solid framework for building your complete testbench environment. One of the main benefits you will find is portability (meaning it would be easy to configure the environment for the next project).
If you are completely starting from scratch I could argue for a pure SV environment. It is easier to manage, maintain and upgrade. Training in one language/methodology has tremendous cost advantages. However since you are planning to reuse some of the C++ code, it may be more efficient to initially settle for a mixed environment. The DPI-C feature in SystemVerilog enables easy interfacing of SV code with pure C code. Using DPI-C you can call “C” routines from SV and vice-versa. The C layer can be used to manage your C++ objects and call appropriate C++ routines.
Thank you very much Logie!
I completely agree with your analysis using a pure SV env.
I have never used C/C++ together with SV, so wanted to get an expert feedback to know what disadvantages/problems I might have with this mixed language environment. Your response certainly gives some confidence.