In my opinion UVM provides a solid framework for building your complete testbench environment. One of the main benefits you will find is portability (meaning it would be easy to configure the environment for the next project).
If you are completely starting from scratch I could argue for a pure SV environment. It is easier to manage, maintain and upgrade. Training in one language/methodology has tremendous cost advantages. However since you are planning to reuse some of the C++ code, it may be more efficient to initially settle for a mixed environment. The DPI-C feature in SystemVerilog enables easy interfacing of SV code with pure C code. Using DPI-C you can call “C” routines from SV and vice-versa. The C layer can be used to manage your C++ objects and call appropriate C++ routines.