module asertion_ex; bit clk=0; bit a; always #5 clk = ~clk; //clock generation //generating 'a' initial begin a=1; #15 a=0; // not working //#14 a=0; // is working #10 a=1; #10 a=0; #10 a=1; #10 a=0; #10 a=1; #10; end //assertion sequence…

In reply to muku_383 : Issue isn’t with #15. //1. assertion sample the value in the prepone region and use that value in deciding the outcome of the assertion //2. Execution of the pass/fail code of concurrent assertions happen in the re-active region. //In between 1 and 2, assignment of the var…

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Why it's not working on #15 delay

SystemVerilog

m_r_m January 22, 2020, 11:44am 3

In reply to Rahulkumar:

sure sir, thank you