Why it's not working on #15 delay

SystemVerilog
,
2

In reply to muku_383:

Issue isn’t with #15.


//1. assertion sample the value in the prepone region and use that value in deciding the outcome of the assertion 
//2. Execution of the pass/fail code of concurrent assertions happen in the re-active region. 
//In between 1 and 2, assignment of the variable a happens.  
// so if you use the $sampled then it will display the value which was used for assertion evaluation. 

a_1: assert property(seq_1)
  $display("success, time: %0t, a: %0d", $time, $sampled(a));
else
  $display("failed, time: %0t, a: %0d", $time, $sampled(a));

I suggest you to go through the SV Scheduling.