Why function new() is used in derived class in UVM testbench?

UVM
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1 


class simple_driver extends uvm_driver#(simple_item);
simple_item item;
virtual dut_if vif;

`uvm_component_utils(simple_driver)
function new(string name = "simple_driver",uvm_component parent);
super.new(name, parent)
endfunction

function build_phase()

endfunction
//

task XYZ();

endtask
//

endclass

My question is, why do we need function new() and what does it do?

Thanks in advance

2

In reply to sriharifoxtrot:

This is a general SystemVerilog requirement. See https://verificationacademy.com/forums/uvm/why-we-need-mention-name-super.newname#reply-88061

For uvm_component, see https://verificationacademy.com/forums/uvm/uvm-component-constructor#reply-75321