Why do we need virtual interface in UVM?

Hello,

Can someone tell me why do we need virtual interfaces in UVM. Basically I would like to understand what is that we can’t do with interfaces which we can do with virtual interfaces ?

Can someone explain the background for the introduction of virtual interface UVM?

Thanks,
Sreedhar.

In reply to Sreedhar Pothuraju:

https://verificationacademy.com/forums/systemverilog/why-do-we-need-virtual-interfaces-system-verilog#reply-52585

See my DVCon paper: The Missing Link: The Testbench to DUT Connection

In reply to dave_59:

Thanks Dave for clarifying this issue.