Why dist constraint doesnt produce exact solution?

SystemVerilog
, , ,
1 
class Transaction;
  rand bit read_write;
  
  constraint c1 { read_write dist {0:= 25, 1:= 25}; }
  
  
  function void pre_randomize();
    $display("Entering randomization \n");
  endfunction
  
  function void post_randomize();
    $display("Done with randomization \n");
  endfunction
endclass

module top;
  
  Transaction tr;
  int write_cnt, read_cnt;
  int constraint_status=0;
  
  initial begin
    tr = new;
    write_cnt = 0;
    read_cnt = 0;
    repeat(100) begin
      assert(tr.randomize());
      constraint_status = tr.c1.constraint_mode();
      if(tr.read_write == 1) write_cnt++;
      else read_cnt++;
    end
    $display("Writes are %d, reads are %d, status is %d \n", write_cnt, read_cnt, constraint_status);
  end
  
endmodule

In the above code, I expect
Writes are 50, reads are 50, status is 1 .
But I get
Writes are 52, reads are 48, status is 1

Why isn’t the constraint solver giving me accurate solution? When I reduce my run count to say small number like 6, I even get strange results

Writes are 2, reads are 4, status is 1

2

In reply to smukerji:

The odds of getting a perfect distribution are very low. Only after a very large number of randomizations will you approach 50%.

See randomisation_dist | Verification Academy and
distributed weightage constraint | Verification Academy

3

In reply to smukerji:

See also https://www.youtube.com/watch?v=NbInZ5oJ0bc for a philosophical perspective.