UVM_ERROR @ 0: uvm_test_top.env.agent.predictor.port_01 [Connection Error] Cannot connect to null port handle
“this is the error and i am not getting that what does this error mean and how can i correct it?”
In reply to chaitanyh shirsh:
This error Messages says clearly the port handle has not been constructed.
In reply to chr_sue:
`include "seq_item.sv";
`include "aes_package.sv";
class aes_subscriber extends uvm_subscriber#(encrypt_seq_item);
`uvm_component_utils(aes_subscriber)
uvm_analysis_port#(encrypt_seq_item) port_1;
//encrypt_seq_item tx;
aes_pkg pkg_1;
// int KEY_LENGTH;
// int ROUNDNO ;
// bit valid_in;
// bit valid_out;
// int key_len=KEY_LENGTH;
// int round_num;
encrypt_seq_item tx;
//uvm_analysis_port#() ap_01;
function new(string name, uvm_component parent);
super.new(name, parent);
tx=new();
port_1 = new("port_1", this);
$display("In the susbcriber block");
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
//bit[KEY_LENGTH - 1] key_in;
//bit[KEY_LENGTH - 1] key_out;
//write(encrypt_seq_item tx);
// uvm_analysis_port#(uvm_sequence_item) ap;
function void write(encrypt_seq_item t);
int k;
tx = t;
if(tx.key_width==128 | tx.key_width == 192 | tx.key_width == 256)
begin
$display("valid key");
end
else
begin
$display("incorrect key length");
end
if(tx.key_width == 128)
begin
k=10;
key_gen_128(k,tx.key,tx.data);
end
else if(tx.key_width == 192)
begin
k=12;
//key_gen_192(k,tx.key,tx.from_file);
end
else if(tx.key_width ==256)
begin
k=16;
// key_gen_256(k,tx.key,tx.from_file);
end
else
begin
$display("not a correct key_width");
end
$display("From Subscriber");
//if(tx.pkt_type == )
//tx.print();
//virtual task encryption;
endfunction:write
function key_gen_128(round_num,key_in,valid_in);
//const int l = key_len;
bit [31 : 0] key_msb_xor_in ;
bit [127 : 0] key_out_int ;
//key_msb_xor_in = {look_up_key(int`(unsigned(key_in[23:16]),look_up_key(int`(unsigned(key_in[15:8]))),look_up_key(int(unsigned(key_in[7:0]))),look_up_key(int(unsigned(key_in[31:24])))}
// key_msb_xor_in = {look_up_key(int`(unsigned`(key_in[23:16])),look_up_key(int`(unsigned(key_in[15:8]))),look_up_key(int(unsigned(key_in[7:0]))),look_up_key(int(unsigned(key_in[31:24])))}
//key_msb_xor_in = look_up_key($rtoi($bitstoreal(unsigned'(key_in)))) ;
key_msb_xor_in = pkg_1.look_up_key[$rtoi($bitstoreal(unsigned'(key_in)))];
$display("key_msb_xor_in is %p", key_msb_xor_in);
//key_out_int[key_len - 1 : key_len - 32] = key_in[key_len -1: key_len-32];
//endtask:encryption
endfunction:key_gen_128
endclass
above is the code of mine …can u suggest why is no port handle is being constructed…
In reply to chaitanyh shirsh:
The error message points to port01 in the following hierarchy
uvm_test_top.env.agent.predictor
But I do not see any env, agent and predictor.
In reply to chr_sue:
THIS IS THE AGENT…
class encrypt_agent extends uvm_agent;
encrypt_sequencer sequencer;
encrypt_driver driver;
encrypt_monitor monitor;
aes_subscriber predictor;
`uvm_component_utils(encrypt_agent);
uvm_analysis_port#(encrypt_seq_item) anal_port2;
uvm_analysis_port#(encrypt_seq_item) analysis_scoreboard_01;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
anal_port2 = new("anal_port2", this);
sequencer = encrypt_sequencer::type_id::create("sequencer", this);
driver = encrypt_driver::type_id::create("driver", this);
monitor = encrypt_monitor::type_id::create("monitor", this);
predictor = aes_subscriber::type_id::create("predictor",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(is_active == UVM_ACTIVE)
driver.seq_item_port.connect(sequencer.seq_item_export);
monitor.anal_port1.connect(anal_port2);
//driver.analysis_scoreboard.connect(predictor.port_01);
predictor.port_1.connect(analysis_scoreboard_01);
endfunction
endclass
THIS IS THE ENVIRONMENT…
``` verilog
`ifndef ENCRYPT_ENV_SV
`define ENCRYPT_ENV_SV
class encrypt_env extends uvm_env;
encrypt_agent agent;
`uvm_component_utils(encrypt_env)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent = encrypt_agent::type_id::create("agent", this);
endfunction
endclass
`endif
****
**THIS IS THE DRIVER**
``` verilog
`include "interface.sv"
`include "seq_item.sv"
class encrypt_driver extends uvm_driver #(encrypt_seq_item);
`uvm_component_utils(encrypt_driver);
uvm_analysis_port#(encrypt_seq_item) analysis_scoreboard;
virtual intf vif; //virtual interface handle...
int file_data;
int file_key;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
analysis_scoreboard = new ("analysis port",this);
endfunction
virtual task run_phase(uvm_phase phase);
`uvm_info("INFO", "Called my_driver::run_phase", UVM_NONE);
super.run_phase(phase);
phase.raise_objection(this);
fork
get_and_drive(phase);
join
endtask
virtual task get_and_drive(uvm_phase phase);
file_key = $fopen("input_drived_to_DUT/key_driver.txt");
file_data = $fopen("input_drived_to_DUT/data_driver.txt");
forever begin
phase.drop_objection(this);
seq_item_port.get_next_item(req);
analysis_scoreboard.write(req); //to write on the analysis port..............
//
$display("recieved key at driver %h, time_delay = %d",req.key, req.valid_time_gap);
phase.raise_objection(this);
$cast(rsp, req.clone());
rsp.set_id_info(req);
$display("Rsp = %d", rsp.valid_time_gap);
drive_transfer(req);
seq_item_port.item_done();
end
$fclose(file_data);
$fclose(file_key);
endtask
virtual task drive_transfer(encrypt_seq_item trans);
begin
@(posedge vif.clk) begin
$display("i am here = %d", trans.valid_time_gap);
// $display("vif.vip_clk.valid_in=%d", vif.vip_clk.valid_in);
vif.vip_clk.valid_in <= trans.valid_in;
if(trans.valid_in) begin
vif.vip_clk.key <= trans.key;
//$display("transaction key in driver = trans.key = %h, vif.vip_clk.key = %h", trans.key, vif.vip_clk.key);
$fwrite(file_key, "%h\n", trans.key);
vif.vip_clk.data <= trans.data;
//$display("transaction data in driver = trans.data = %h, vif.vip_clk.data = %h", trans.data, vif.vip_clk.data);
$fwrite(file_data, "%h\n", trans.data);
end
repeat(trans.valid_time_gap)@(posedge vif.clk)begin
vif.vip_clk.valid_in <= 0;
end
end
trans.valid_out = vif.vip_clk.valid_out;
end
endtask
endclass
**plzz take a view…
**
In reply to chaitanyh shirsh:
In the agent you do not construct analysis_scoreboard_01.
But in the connect_phase you try to connect
predictor.port_1.connect(analysis_scoreboard_01);
My question is why do you need 2 Analysis ports in the Agent? Do you really provide 2 different transaction for analysis?
In reply to chr_sue:
actually i am making a refference model of my design and i am first connecting it to the agent to check it and then later i will connect it to my scoreboard…
and the 2nd analysis port is to connect the monitor to the agent.
In reply to chaitanyh shirsh:
ELAB2_0036 Unresolved hierarchical reference to “driver.analysis_scoreboard_01.connect./0/” from module “encrypt_agent” (module not found).
what can be the reason of this error?
if my code of agent is as follows:-
class encrypt_agent extends uvm_agent;
encrypt_sequencer sequencer;
encrypt_driver driver;
encrypt_monitor monitor;
aes_subscriber predictor;
`uvm_component_utils(encrypt_agent);
uvm_analysis_port#(encrypt_seq_item) anal_port2;
uvm_analysis_port#(encrypt_seq_item) analysis_scoreboard_01;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
anal_port2 = new("anal_port2", this);
analysis_scoreboard_01 = new("analysis_scoreboard_01",this);
sequencer = encrypt_sequencer::type_id::create("sequencer", this);
driver = encrypt_driver::type_id::create("driver", this);
monitor = encrypt_monitor::type_id::create("monitor", this);
predictor = aes_subscriber::type_id::create("predictor",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(is_active == UVM_ACTIVE)
driver.seq_item_port.connect(sequencer.seq_item_export);
monitor.anal_port1.connect(anal_port2);
//driver.analysis_scoreboard.connect(predictor.port_01);
driver.analysis_scoreboard_01.connect(predictor.analysis_export);
$display("connection of the agent to the subscriber");
endfunction
endclass
In reply to chaitanyh shirsh:
Does your predictor have an analysis_export?
In reply to chr_sue:
I got rid of the problem ,actually subscriber do have a by default export and i don’t need to connect the predictor using the new analysis port .
it can be directly connected using the export.
thanks for ur help…