In reply to chr_sue:
THIS IS THE AGENT…
class encrypt_agent extends uvm_agent;
encrypt_sequencer sequencer;
encrypt_driver driver;
encrypt_monitor monitor;
aes_subscriber predictor;
`uvm_component_utils(encrypt_agent);
uvm_analysis_port#(encrypt_seq_item) anal_port2;
uvm_analysis_port#(encrypt_seq_item) analysis_scoreboard_01;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
anal_port2 = new("anal_port2", this);
sequencer = encrypt_sequencer::type_id::create("sequencer", this);
driver = encrypt_driver::type_id::create("driver", this);
monitor = encrypt_monitor::type_id::create("monitor", this);
predictor = aes_subscriber::type_id::create("predictor",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(is_active == UVM_ACTIVE)
driver.seq_item_port.connect(sequencer.seq_item_export);
monitor.anal_port1.connect(anal_port2);
//driver.analysis_scoreboard.connect(predictor.port_01);
predictor.port_1.connect(analysis_scoreboard_01);
endfunction
endclass
THIS IS THE ENVIRONMENT…
``` verilog
`ifndef ENCRYPT_ENV_SV
`define ENCRYPT_ENV_SV
class encrypt_env extends uvm_env;
encrypt_agent agent;
`uvm_component_utils(encrypt_env)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent = encrypt_agent::type_id::create("agent", this);
endfunction
endclass
`endif
****
**THIS IS THE DRIVER**
``` verilog
`include "interface.sv"
`include "seq_item.sv"
class encrypt_driver extends uvm_driver #(encrypt_seq_item);
`uvm_component_utils(encrypt_driver);
uvm_analysis_port#(encrypt_seq_item) analysis_scoreboard;
virtual intf vif; //virtual interface handle...
int file_data;
int file_key;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
analysis_scoreboard = new ("analysis port",this);
endfunction
virtual task run_phase(uvm_phase phase);
`uvm_info("INFO", "Called my_driver::run_phase", UVM_NONE);
super.run_phase(phase);
phase.raise_objection(this);
fork
get_and_drive(phase);
join
endtask
virtual task get_and_drive(uvm_phase phase);
file_key = $fopen("input_drived_to_DUT/key_driver.txt");
file_data = $fopen("input_drived_to_DUT/data_driver.txt");
forever begin
phase.drop_objection(this);
seq_item_port.get_next_item(req);
analysis_scoreboard.write(req); //to write on the analysis port..............
//
$display("recieved key at driver %h, time_delay = %d",req.key, req.valid_time_gap);
phase.raise_objection(this);
$cast(rsp, req.clone());
rsp.set_id_info(req);
$display("Rsp = %d", rsp.valid_time_gap);
drive_transfer(req);
seq_item_port.item_done();
end
$fclose(file_data);
$fclose(file_key);
endtask
virtual task drive_transfer(encrypt_seq_item trans);
begin
@(posedge vif.clk) begin
$display("i am here = %d", trans.valid_time_gap);
// $display("vif.vip_clk.valid_in=%d", vif.vip_clk.valid_in);
vif.vip_clk.valid_in <= trans.valid_in;
if(trans.valid_in) begin
vif.vip_clk.key <= trans.key;
//$display("transaction key in driver = trans.key = %h, vif.vip_clk.key = %h", trans.key, vif.vip_clk.key);
$fwrite(file_key, "%h\n", trans.key);
vif.vip_clk.data <= trans.data;
//$display("transaction data in driver = trans.data = %h, vif.vip_clk.data = %h", trans.data, vif.vip_clk.data);
$fwrite(file_data, "%h\n", trans.data);
end
repeat(trans.valid_time_gap)@(posedge vif.clk)begin
vif.vip_clk.valid_in <= 0;
end
end
trans.valid_out = vif.vip_clk.valid_out;
end
endtask
endclass
**plzz take a view…
**