While loop logic

SystemVerilog
, ,
1

Hi all,

I am trying to read back the FSM status registers, using while loop. Basically i have 3 FSM’s running parallel independent of one another , I want to exit out of the while lopp when all the 3 FSM state (reg_rdbk_value[4:0], reg_rdbk_value[12:8],reg_rdbk_value[20:16]) has reached state='d14. But currently with following code when one of FSM state reaches 'd14 , it is exiting out .

Please can you point where i am going wrong or better logic can be implemented .


bit [31:0] reg_rdbk_value;
task run_phase(uvm_phase phase)
....
begin
   while((reg_rdbk_value[4:0] !== 'd14) && (reg_rdbk_value[12:8] !== 'd14) && (reg_rdbk_value[20:16] !== 'd14)) begin
     reg_blk_h.fsm_reg_h.read(.value(reg_rdbk_value),.status( status ),.path(UVM_FRONTDOOR));
   end
  disable_phy();
end

endtask

Thank you

2

In reply to rohit_kumar:

Convert those &&'s into ||'s.