While(1) vs always vs forever

SystemVerilog
1

Hello forum gurus!
I have a noob question.
what is the instrinc difference between the following statements in sv?

always @(posedge clk) begin
  //code
end

while(1) begin
  @(posedge clk);
  //code
end

forever begin
  @(posedge clk);
  //code
end

besides, is it possible to use loop control like break/ continue in the forever loop?

2

In reply to pepes:

See always block in task | Verification Academy

Yes, you can use break/ continue in a forever loop