Which will be influnced by the static bit use_uvm_seeding?

UVM
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The use_uvm_seeding is a static bit veriable in the uvm_object.svh source code, the default value is 1. The description of it is that it will affects the function reseed(). But I try call the fuction for a subclass of uvm_object where I make the use_uvm_seeding=0. The result of the subclass is different in two sim.

So, I wish to know which will be affected by the use_uvm_seeding=0? Does it really will affect the random function ?

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In reply to jasonyu199212:

Can you share a small example?

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In reply to dave_59:
there is an example:

cfg_blk=disp_dsc_cfg_blk::type_id::create("cfg_blk");
               cfg_blk.reseed();
               `uvm_info(get_name();{"...",this.cfg_blk.sprint()},UVM_LOW);

I found the value of the cfg_blk is different in two simulatin. While the variables’ value in cfg_blk are all zero. Thus, I think the use_uvm_seeding=0 will make the variables no random anymore, but the cfg_blk may be influenced by the sim env.

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In reply to jasonyu199212:

That is a code snippet, not a complete example.