Which will be influnced by the static bit use_uvm_seeding?

UVM
, , ,
3

In reply to dave_59:
there is an example:

cfg_blk=disp_dsc_cfg_blk::type_id::create("cfg_blk");
               cfg_blk.reseed();
               `uvm_info(get_name();{"...",this.cfg_blk.sprint()},UVM_LOW);

I found the value of the cfg_blk is different in two simulatin. While the variables’ value in cfg_blk are all zero. Thus, I think the use_uvm_seeding=0 will make the variables no random anymore, but the cfg_blk may be influenced by the sim env.