Dear friend, I have 2 question regarding to the Synthesis. First, Can anyone specify that which SystemVerilog syntax can be synthesized? As an example, I want to know that the following line can be synthesized? parameter g = 7'b5; Second, What is the difference between the parameter and reg f…

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Which syntax can be Synthesized?

SystemVerilog

Mahdiyar September 1, 2016, 9:24am 5

In reply to sumitwankhade:

Thank you for the explanation.