What kind of issues I will see when I move from block level to full-chip level verification from a design verification perspective

UVM
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What kind of issues I will see when I move from block level to full-chip level verification from a design verification perspective

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In reply to GC:

There is no clear answer. It depends of the details you are facing. If you have still access to the functional interfaces it is simply adding more agents to your env. Assumed your blocklevel env allows reuse.
And your scoreboard functionality becomes more complex.
If your functional interfaces become internal interfaces it becomes a lot more complicated. Because you have to resolve this topic.