What is UVM generator?

UVM
1

Can you please share me the pointer to generators in UVM. (Is driver and generator the same?)

2

In reply to chiranji.vamshidhar:

It would help if you provide a link to where you saw the term “generator” Usually it refers to “stimulus generator” in the form of transactions that it constructs and sends to a driver. A “driver” is an abstraction converter. It translates transactions that are usually a packet of a combination of commands and data into a lower level abstraction, usually in a form that the DUT can understand.

3

In reply to chiranji.vamshidhar:

2 guess works (in the absence of OP not showing the source of this term “generators”)

  1. Plain SV, VMM and the likes used this term. Equivalent here is sequencer, though really the generation is done inside sequence body and tunnelled through SQR-Driver.

  2. There are some “generators” of UVM code base. This would generate/create a full set of UVM components, interface, assertions etc. It could also create scripts for various EDA tools. One such generator is from our new venture VerifWorks.com and is freely available for download at: http://verifworks.com/products/dvcreate-uvm/

HTH
Srini
www.verifnews.org

4

In reply to Srini @ CVCblr.com:

For UVM-MS I use the term “generator” and 'analyzer" for the elements of the “translator” communicates between the UVM agent and an analog interface to (or inside) the DUT.

for these blocks we DON’t want to use the term “driver” or “monitor” because those terms are already used for the elements inside an agent.

I may be the only one using it this way, but I’ve been using this term for several years now, since I realized the need for something between the system Verilog types and the signals use for analog signals (ie Verilog-AMS or Verilog-A electrical or perhaps even the new SV-2012 User defined types.)