Hello,
If a signal is changing from 0 to 1 at time t1 and assume that I have code
if(signal === 1){
Some code
}
Will this if condition evaluate to true at the exact time t1.
Thanks
Hello,
If a signal is changing from 0 to 1 at time t1 and assume that I have code
if(signal === 1){
Some code
}
Will this if condition evaluate to true at the exact time t1.
Thanks
In reply to sj1992:
Not always true, it depends on where do you put the above code to monitor the signal.
If the code is not executed at right time (maybe after the signal asserts), it will never meet the condition. Normally, I usually use “wait” statement if I want to check a signal is asserted at specific time. Or you can loop with clock event to check the signal.
In reply to sj1992:
In discrete event driven simulation, like SystemVerilog, no two events happen simultaneously. Either the signal changes first, or the condition evaluates first.
If there are multiple processes involved, there are a number of things you can do to guarantee a specific ordering. The easiest would be to use a non-blocking assignment you your signal.
In reply to dave_59:
Also, see discussion and my reply on various SV evaluation regions at
https://verificationacademy.com/forums/systemverilog/sampling-point-assertions
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to dave_59:
In reply to sj1992:
In discrete event driven simulation, like SystemVerilog, no two events happen simultaneously. Either the signal changes first, or the condition evaluates first.
If there are multiple processes involved, there are a number of things you can do to guarantee a specific ordering. The easiest would be to use a non-blocking assignment you your signal.
As per your answer related to the concept of execution, I’ve one query regarding execution inside constraint(constraint solver).
if constraint like c_one is given
constraint c_one {(b=0) → (c=1) ;} //bit b, c ;
then how it’ll decide that firstly it has to solve b and then c? or how does it solve this constraint?
As this means that if b=0 then only c=1, and you’ve said that Either the signal changes first, or the condition evaluates first.
How constraint solver will solve this?
Please explain w.r.t. timestamp.
In reply to Mittal Maru:
Constraints are boolean expressions that do not involve time. You can replace the implication operator with the equation (b==1 || c==1). The solver just need to pick values for b and c that make the equation true.