In reply to dave_59:
In reply to sj1992:
In discrete event driven simulation, like SystemVerilog, no two events happen simultaneously. Either the signal changes first, or the condition evaluates first.
If there are multiple processes involved, there are a number of things you can do to guarantee a specific ordering. The easiest would be to use a non-blocking assignment you your signal.
As per your answer related to the concept of execution, I’ve one query regarding execution inside constraint(constraint solver).
if constraint like c_one is given
constraint c_one {(b=0) → (c=1) ;} //bit b, c ;
then how it’ll decide that firstly it has to solve b and then c? or how does it solve this constraint?
As this means that if b=0 then only c=1, and you’ve said that Either the signal changes first, or the condition evaluates first.
How constraint solver will solve this?
Please explain w.r.t. timestamp.