What is "Hierarchical Constraints" in system verilog?

SystemVerilog
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1

Hi,

Can anybody explain me what is “hierarchical constraints” in system verilog ?

Thanks in advance.

Regards,
Chetan Shah

2

In reply to cashah85:

Hello,

I’m not sure if you have found this paper online http://events.dvcon.org/2015/proceedings/papers/04P_11.pdf

It explains the concept from the paper itself which in the LRM is referred as Global constraints

“… A class may declare an object
member (i.e. class instance) as “rand”. When the top-level object is randomized, the lower level objects are also randomized. All rand variables and constraints in the top- and lower-level objects are solved simultaneously…”

The exact example from the IEEE 1800-2012 SV LRM section 18.5.9 Global constraints
“…Constraint expressions involving random variables from other objects are called global constraints…”

class A; 
rand bit [7:0] v;
endclass
class B extends A;
rand A left;
rand A right;
constraint heapcond {left.v <= v; right.v > v;}
endclass

In this code when you randomise an instance of B the solver will solve B and its left and right children simultaneously.

I hope this is what you meant by hierarchical constraints.
-R