What code goes into main_phase

UVM
, ,
1

Hi,

Can someone tell me what code goes into end_of_elaboration, start_of simulation, and main_phase? I saw that TB topology and opening of log files are done in start_of_simulation phase. I also have not come across extract and check phase in any of the examples I have seen so far. Do we really need these extract and check phases?

Thanks.

2

In reply to sj1992:

We do not recommend using the main_phase for the very reason you are asking this question. Since there is no standard way of defining what goes in each phase, it becomes difficult to manage. This is especially a problem for the task based phases that execute in parallel with the run_phase. The other function based phases become just a convenience to execute code in a particular ordering at time 0 or at the end of simulation.

3

In reply to dave_59:

Thanks Dave. But in most of the designs we are required to bring the system to default state using Reset. To do this in UVM do we write the Reset functionality in reset_phase or is it ok to include the Reset functionality in run_phase. And also can you explain what code goes into end_of_elaboration phase. I have seen some vague explanations like “Used to make any final adjustments to the structure, configuration or connectivity of the testbench before simulation starts.”

Thanks.

4

In reply to sj1992:

In most applications it is sufficient to deal with the run_phase. In this phase you can execute anything in a corresponding order. If you need first a RESET, then execute first a reset sequence, followed by configuration sequence and then the operationaöl sequences.

5

In reply to chr_sue:

Thanks chr_sue. Can you also tell what is the use of end_of_elaboration phase?

Thanks.

6

In reply to sj1992:

The end_of_elaboration phase and the start_of_simulation phase are functions, i.e. they do not consume any time. In these phases you can perform certain checks related to the UVM environment and you can specify settings for the environment.

7

In reply to sj1992:
We do not recommend using the main_phase for the very reason you are asking this question. Since there is no standard way of defining what goes in each phase, it becomes difficult to manage. This is especially a problem for the task based phases that execute in parallel with the run_phase. The other function based phases become just a convenience to execute code in a particular ordering at time 0 or at the end of simulation.

Hi Dave, why do uvm need to define preset,reset,main,shutdown etc in run phases?
Can i just use run in run phases to verify dut?
what is the difference between run and other in the run phase?
Thanks a lot!!!


In reply to dave_59:

8

In reply to peter:

You can just use the run_phase with sequences defining the steps needed.