In reply to dave_59:
Thanks Dave. But in most of the designs we are required to bring the system to default state using Reset. To do this in UVM do we write the Reset functionality in reset_phase or is it ok to include the Reset functionality in run_phase. And also can you explain what code goes into end_of_elaboration phase. I have seen some vague explanations like “Used to make any final adjustments to the structure, configuration or connectivity of the testbench before simulation starts.”
Thanks.