Ways to define Look Up Tables of enum types in SystemVerilog -> how to?

SystemVerilog
1

Hi All,

I need to declare the following Look Up Table:
…C2 … C1 … C0
L0…t0 … t1 … t2
L1…t2 … t1 … t0
L2…t1 … t0 … t2

where t0, t1 and t2 are enum elements of the LUT.

Each element of the LUT should be referenced by (L*,C*), which are also of enum type.

Ex:
LUT(C2,L0) should refer to t0
LUT(C1,L1) should refer to t1
LUT(C0,L2) should refer to t2

So, how should I define this LUT? How should I refer the elements in the LUT?

Thank you!

2

In reply to dmitryl:

typedef enum {C[0:2]} C_e;
typedef enum {L[0:2]} L_e;
typedef enum {t[0:2]} t_e;

t_e LUT[L_e][C_e];

LUT = '{L0:'{C2:t0, C1:t1, C0:t2}, 
        L1:'{C2:t2, C1:t1, C0:t0},
        L2:'{C2:t1, C1:t0, C0:t2} };

// or
LUT[L0][C0] = t0;
LUT[L0][C1] = t1;
...
3

In reply to dave_59:

Is there a way to define a type of/for the LUT using typedef ?

Could it be written as following?

typedef enum t_e[L_e][C_e] LUT_e;

and then to declare the LUT array:
LUT_e LUT;

And one another thing… According to to your example, C[0] is the same as C0… Is that true?

The elements of C_e are C[0], C[1], C[2] or C0, C1, C2**?**

And one another thing… :-)

If I would define C_e as typedef enum {a,b,c} C_e; then could LUT be defined in the same maner as you wrote:
t_e LUT[L_e][C_e];

Your help is appreciated