Ways to define Look Up Tables of enum types in SystemVerilog -> how to?

SystemVerilog
2

In reply to dmitryl:

typedef enum {C[0:2]} C_e;
typedef enum {L[0:2]} L_e;
typedef enum {t[0:2]} t_e;

t_e LUT[L_e][C_e];

LUT = '{L0:'{C2:t0, C1:t1, C0:t2}, 
        L1:'{C2:t2, C1:t1, C0:t0},
        L2:'{C2:t1, C1:t0, C0:t2} };

// or
LUT[L0][C0] = t0;
LUT[L0][C1] = t1;
...