Virtual function in system verilog

UVM
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5

In reply to dave_59:

Understand, Thanks.

Can I add a coverage_top that will be like a top of all coverage classes, and in the env I will instance the coverage top ?
Is it ok that this coverage_top will be also the top of coverage classes, I mean will instance them, and also all coverage classes will extends him. is it makes sense ?

I will how what I’m meaning:

coverage_top:


class coverage_top extends uvm_component;
 
    int reg_addr;
    int reg_data;
    uvm_analysis_imp #(uvm_reg_item, coverage_top )   in_ap;
 
    base_coverage cov1;
    base_coverage cov2;

    `uvm_component_utils(coverage_top )
 
    function new(string name, uvm_component parent= null);
        super.new(name, parent);
        in_ap     = new("in_ap",  this);
    endfunction : new
 

    function void build_phase(uvm_phase phase);
        supeer.build_pahse(phase);
        cov1       = coverage1::type_id::create("cov1",this);  
        cov2       = coverage2::type_id::create("cov2",this);  
    endfunction : build_phase

 
    function void write(uvm_reg_item t);
        uvm_reg r;    
        $cast(r,t.element);       
        reg_addr = r.get_address();
        reg_data = r.get();    
        sample_register_coverage();       
    endfunction
 
 
    virtual function void sample_register_coverage();
        `uvm_info(get_type_name(),  "coverage_top ::sample_register_coverage ", UVM_MEDIUM)        
    endfunction : sample_register_coverage
 
endclass

coverage1:


class coverage1 extends coverage_top;
 
    `uvm_component_utils(coverage1 )
 
    function new(string name, uvm_component parent= null);
        super.new(name, parent);
    endfunction : new
 
    function void sample_register_coverage();
        `uvm_info(get_type_name(),  "coverage1 ::sample_register_coverage ", UVM_MEDIUM) 
    endfunction : sample_register_coverage
 
endclass

env:



class env extends uvm_component;
 
    coverage_top cov_top;
    reg_monitor reg_mon;

    `uvm_component_utils(env )
 
    function new(string name, uvm_component parent= null);
        super.new(name, parent);
    endfunction : new
 
    function void build_phase(uvm_phase phase);
        super.build_pahse(phase);
        cov_top= coverage_top::type_id::create("cov_top",this); 
        reg_mon    = reg_monitor::type_id::create("reg_mon",this);
    endfunction : build_phase
 
    function void connect_phase(uvm_phase phase);
        reg_mon.reg_ap.connect(cov_top.in_ap);
    endfunction : connect_phase
 
endclass

Is this the correct way to do it?
If no, what will be the correct one ?
I want to have 1 connection of the analysis port and 1 implementation task of the related “write” , and few sample_register_coverage implementations - different for each coverage class 1…N

I believe there should be a way.