Virtual function in system verilog

UVM
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2

In reply to AL_verification:

You are confusing child-parent object relationships with inheritance. In the UVM, parent objects (env) create their children (base_cov, cove_child1, cov_child2, reg_mon). coverage_child1 is an extension of base_cov, not a child of it. Would be better to rename coverage_child1 to just coverage1. Then what you probably wanted to write is

class env extends uvm_component;
 
    base_coverage base_cov;
    reg_monitor reg_mon;
    `uvm_component_utils(env)
 
    function new(string name, uvm_component parent= null);
        super.new(name, parent);
    endfunction : new
 
    function void build_phase(uvm_phase phase);
        base_cov   = coverage1::type_id::create("cov_child1 ",this);  
        reg_mon    = reg_monitor::type_id::create("reg_mon",this);
    endfunction : build_phase
 
    function void connect_phase(uvm_phase phase);
        reg_mon.reg_ap.connect(base_cov.in_ap);
    endfunction : connect_phase
 
endclass