VHDL entity with the UVM environment

UVM
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1

How to interface a VHDL entity with the UVM environment? If possible please mention an example, How to port a RECORD type in VHDL?

2

This will depend on your simulator. If you are using Questa, see the User Manual section SystemVerilog Instantiating VHDL and the section Sharing User Defined Types.

3

In reply to dave_59:

I’m using VCSMX…