Verilog RTL code bug for 1-bit counter

SystemVerilog
1

Hi All,
I am trying to write RTL code for 1-bit counter(Reversible T-Flip Flop - Figure1) as given below.
However the output is not toggling as intended(q= 0,1,0,1,0), could you please help in understanding the problem in the code. Thanks in advance!
Figure 1:
Your text to link here…
Feynman gate Truth Table: Your text to link here…
Tofoli Gate Truth Table: Your text to link here…
RTL Code:

module feynman_gate(a,b,p,q,reset);
input a, b, reset;
output reg p,q;
    always@(a, b, reset)
      begin 
    if (reset) 
      begin
       p = 0;
       q = 0;
    end 
    else begin
       p = a;
       q=a^b;
    end 
    end 
endmodule

module toffoli_gate(a, b, c, p, q, r, reset);
input a, b, c, reset; 
output reg p, q, r;
  always@(a, b, reset) begin 
        if(reset) begin
            p = 0;
            q = 0;
            r = 0;
        end 
        else begin
            p = a;
            q = b;
            r =(a&b) ^ c;
       end 
    end
endmodule

module one_bit(t_i, clk, q0, reset);
input t_i, clk, reset;
output q0;
wire gl, g2, o1, en;
  toffoli_gate t1 (.a(t_i), .b(clk), .c(en) , .p(g1), .q(g2), .r(o1), .reset (reset));
  feynman_gate f1 (.a(o1), .b(1'b1), .p(q0), .q(en), .reset (reset));
endmodule

module tb;
wire q0;
bit clk, t_i;
bit reset;
one_bit DUT (.t_i (t_i), .clk(clk), .q0(q0), .reset (reset) );
    initial begin
       reset = 1;
       t_i = 1;
       clk = 1;
      repeat (20) begin
          #10;
          reset = 0;
          clk = ~clk;
       end 
       $finish();
    end
    initial
      $monitor ("VALUES OF clk=%0d t_i=%0d reset=%0d q0=%0d",clk,t_i,reset,q0);
endmodule

OUTPUT:

VALUES OF clk=1 t_i=1 reset=1 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=0
VALUES OF clk=1 t_i=1 reset=0 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=1
VALUES OF clk=1 t_i=1 reset=0 q0=1
VALUES OF clk=0 t_i=1 reset=0 q0=0
VALUES OF clk=1 t_i=1 reset=0 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=1
VALUES OF clk=1 t_i=1 reset=0 q0=1
VALUES OF clk=0 t_i=1 reset=0 q0=0
VALUES OF clk=1 t_i=1 reset=0 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=1
VALUES OF clk=1 t_i=1 reset=0 q0=1
VALUES OF clk=0 t_i=1 reset=0 q0=0
VALUES OF clk=1 t_i=1 reset=0 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=1
VALUES OF clk=1 t_i=1 reset=0 q0=1
VALUES OF clk=0 t_i=1 reset=0 q0=0
VALUES OF clk=1 t_i=1 reset=0 q0=0
VALUES OF clk=0 t_i=1 reset=0 q0=1
2

In reply to Harish_G:

Please use code tags making your code easier to read. I have added them for you.

It also seems you manually retyped your code rather than copy/pasting it. There are many typos. Please correct these before asking someone to look at your code.

3

In reply to dave_59:

Hi Dave!

Thanks for suggesting code tags, its makes the code lot more readable, I will use it consistently in this forum going forward.

I have fixed the typos, Could you please help in identifying the issue in the above code and it would be really helpful.

Thanks!

4

In reply to Harish_G:

Thanks for correct and most of the typos, but there are still a few left. : → ;, l’bl → 1’b1, - → ~.

Your problem is simply you did not run the simulation long enough. You have repeat(5) and you need at least repeat(10) to see q toggle.

5

In reply to dave_59:
Hii Dave, the code is finally getting executed without any syntax errors!!
However as seen from the output we are not able to see one bit toggle instead two bit toggle is seen though the iteration is increased to twenty.
Could you please share your thoughts on it.
Thanks!!