Verilog code for counting pulse not edges (posedge-->negedge, negedge-->posedge)

SystemVerilog
,
1

can anyone help me to write a code for this?
i have written below code…

module counter(clk, rst, enable, count);

input(clk, rst, enable);
output(count);
reg [7:0] count;

always @(posedge clk or negedge rst)
If (!rst) begin
count<=8’b0
end
else if (enable) begin
count<=count + 1
end
endmodule

2

In reply to shravani_k:


//verilog code for counting pulse not edges (posedge-->negedge, negedge-->posedge)
// My interpretation of the requirements: 
//    Increment the count when signal d goes from a 0 to a 1. 
// In SystemVerilog 
module pulse_counter(input bit clk, rst_n, enable, d, 
                     output int count); 
always @(posedge clk)
    if (!rst_n) count<=8'b0;
    else if (enable && $rose(d)) 
       count<=count + 1'b1; 
    ap: assert property(@(posedge clk) disable iff(rst_n==0)
               $rose(d) |-> ##1 count==$past(count) +1'b1);  
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to shravani_k:

I believe this can be simply achieved by replacing posedge clk with clk, it looks for both edges of clk.

always @(clk or negedge rst)
If (!rst) begin
count<=8'b0
end
else if (enable) begin
count<=count + 1
end

Thanks,
Juhi Patel
https://www.linkedin.com/in/juhi-patel-455535149/