Verilog and systemverilog event schedular

SystemVerilog
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1

Hi, While reading the Verilog and systemverilog event schedular, I saw there is feedback from lower regions to upper regions is there any specific reason for that?

you can check in the diagram it is in this paper:-
http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

Thanks.

2

In reply to m_v:
The situation here is that with the exception of the read-only preponed, observed, and postponed regions, every other region may schedule more events. Time can only advance when all event regions in the current time-slot are empty.

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In reply to dave_59:

Can you give more information about this,I am not able to understand.

4

In reply to m_v:

All most users need to understand are the active, inactive, and NBA regions. If you use assertions or clocking blocks, you might also need to know about the observed and re-active regions. Just search for Verilog event scheduling for more information.