what is difference between Verifying a RTL (in which we have dut)… and Devloping a VIP(In which we dont have have any dut) ??
In reply to ImPSharma:
what is difference between Verifying a RTL (in which we have dut)… and Devloping a VIP(In which we dont have have any dut) ??
- RTL has specific requirements on interfaces and configurations.
- RTL has a testbench defined for its specific applications
- VIP has requirements that must adapt to various applications
- VIP must be able to be configured for these possible applications and restrictions
- VIP testbench must be flexible enough to adapt to these configurations.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
In reply to ImPSharma:
- RTL has specific requirements on interfaces and configurations.
- RTL has a testbench defined for its specific applications
- VIP has requirements that must adapt to various applications
- VIP must be able to be configured for these possible applications and restrictions
- VIP testbench must be flexible enough to adapt to these configurations.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
Thanks for the answer…
In Verifying dut,we’ve dut so we send data to dut and check the correctness.
but,in Devloping VIP,we don’t have DUT,the what we do, ??
that’s my question.
In reply to ImPSharma:
In Verifying dut,we’ve dut so we send data to dut and check the correctness.
but,in Devloping VIP, we don’t have DUT, the what we do, ??
that’s my question.
Good question. However, like verifying any design partition (e.g., a targeted VIP, like AMBA, ALU, EDAC, etc), you define a BFM, or an environment around that targeted VIP. Thus, in essence, in verifying a VIP, the “DUT” is really the BFM needed. The difference here though is that the BFM that surrounds the VIP can be at a higher level of abstraction. For example, to verify a VIP that is an EDAC, the verification environment can be a set of tables or just a set of constrained-random tests that creates stimuli with and without forced errors, and verifying that the VIP does indeed provide the expected responses.
Bottom line, I think of a VIP as just another design partition. Question to you, how do you verify a design partition?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us