In reply to ImPSharma:
what is difference between Verifying a RTL (in which we have dut)… and Devloping a VIP(In which we dont have have any dut) ??
- RTL has specific requirements on interfaces and configurations.
- RTL has a testbench defined for its specific applications
- VIP has requirements that must adapt to various applications
- VIP must be able to be configured for these possible applications and restrictions
- VIP testbench must be flexible enough to adapt to these configurations.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115