Verification of changing pulse width signal and the repetation sequence

SystemVerilog
1

Hi,

Following is the signal behavior of sig_x:

  1. First rising edge of sig_x is seen after n clock cycles
  2. The signal goes high and low alternatively like a clock does but every 32nd pulse is 1 clock cycle more than other 31 pulses.
    For eg: lets say the pulse width of sig_x is 100 clock cycles. 31 consecutive high and low pulses are 100 clock cycles wide, and 32nd pulse is 101 clock cycles wide. This behavior of 32 pulses occurs 11 times and sig_x goes low after that.
  3. sig_x is in sync with clock

I am trying to verify this behavior using SVA as follows:

sequence standard;
	$changed(sig_x) ##1 $stable(sig_x)[*99] ##0 $changed(sig_x);
endsequence

sequence long_low;
	$fell(sig_x) ##1 $stable(sig_x)[*100] ##0 $rose(sig_x);
endsequence

property verify_sig_x;
	(standard)[*31] ##0 (long_low);
endproperty
 
assert property (@(posedge clk)verify_sig_x)
	`uvm_warning("test", "warn: test running")
	 else
	`uvm_error("test", "error: failed test")

Seems like this is not working as expected. Can anyone provide more input on solving this problem?

-Sunshine

2

what error are you getting ? or are you expecting an error but not getting one?
if 31 consecutive high and low pulses are 100 clk cycles wide then shoudnt you be looking for both high and low?

i.e

sequence standard;
	$rose(sig_x) ##1 $stable(sig_x)[*99] ##0 $fell(sig_x)##1 $stable(sig_x)[*99] ##0 $rose(sig_x);
endsequence

also the thirty first is again a rose and fell cycle with 101 cycles correct?

3

In reply to sohan_b:

Thanks Sohan for looking into this.

The ‘error: failed test’ gets fired every posedge of clock. I am expecting it not to fire the error given the behavior of the signal.

Also, to answer your question - “if 31 consecutive high and low pulses are 100 clk cycles wide then shoudnt you be looking for both high and low?”; I am using $changed so that it takes care of both rising and falling edges.

The 32nd pulse is only a low pulse that is 101 clk cycles, and hence I am using $fell and $rose here.

4

ok thanks, does the assertion fire right after 1st clock? or 100 clocks? can you paste the full string? from “offending”

Also, on a second thought I think its a bad idea to expect a signal to evalualte both $stable and $rose/fell in a conjuction.

so this $stable[*99] ##0 $fell will always be false as it cant be stable and fell in the same clock.

instead try $stable[*98] ##1 $fell

5

In reply to sohan_b:

[quote] Also, on a second thought I think its a bad idea to expect a signal to evalualte both $stable and $rose/fell in a conjuction.

In the above case, the $stable or $changed or $fell tasks are evaluating the status of the signal and signal itself has nothing to do with this. I am guessing you can evaluate the same signal with multiple tasks based on what one is expecting at that point.

I agree with your following notation and tried it.

But this doesn’t seem to work too.

Following is the piece of code that I tried:

sequence standard;
$changed(siq_x) ##1 $stable(sig_x)[*98] ##1 $changed(sig_x);
endsequence

sequence long_low;
$fell(sig_x) ##1 $stable(sig_x)[*99] ##1 $rose(sig_x);
endsequence

property verify_sig_x;
(standard)[*31] |=> (long_low);
endproperty

assert property (@(posedge clk)verify_sig_x)
uvm_warning("test", "warn: test running") else uvm_error(“test”, “error: failed test”)

This time, the assertion itself is not being evaluated. No errors or warnings.