In reply to Maitri@07:
In reply to ben@SystemVerilog.us:
Hi Ben,
I have a doubt . If you use only one agent , one driver , one sequencer then how will you drive read and write operations simultaneously ?
If you have 1 agent then you get interleaved seq_items, starting maybe with RD followed by WR. If you have a real dual port RAM which allows RD and WR at the same time, then you need 2 agents. But I’d not say a RD agent and a WR agent. I’d design only 1 agent but instantiate the same agent twice, each connected to the corresponding virtual interface.