Varifying a complete system including PL and PS

UVM
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Hi everyone.

I am new to Vivado and I want to test my design which is a many-core platform consists of 10 Nodes (Processes).
I know I am not going to test the whole design but I should be able to test a single node.
The question is how can I test a single node that has PL and PS parts. Also I need to be able to ABV to test the components such as the Router, SPI and drivers.

Simply I need to write one testBench to test the whole ssytem including PL and PS.

Thanks

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In reply to Abuassal:

Could you please explain what is PL and PS?

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In reply to chr_sue:

Hi CHr_sue,

Thanks for the reply.

Sorry I have forgot to mention that, I am using Zynq Board, So it has Programming Logic part (FPGA) and Processing System (ARM processor). So the project is on both.

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In reply to Abuassal:

OK, I understand. The question is now what Kind of testbench you want to implement.Do you look for a UVM testbench or a traditional one. UVM requires special licenses for Simulation. Do you have them?

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In reply to chr_sue:

I would use UVM if the University agree to pay for the licenses because my PhD project is funded. However, so far I can use a traditional TB.

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In reply to Abuassal:

If you want to use UVM I’m recommending to use a UVM Framework Generator. A useful version free of charge is provided by Doulos. There are also coding guidelines included.
For details see Doulos.
To get a first impression how a UVM Environment is looking like please visit my webpage at
www.christoph-suehnel.de.

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In reply to chr_sue:

That’s great, thank you so much.

But can I ask again is it even possible to verify the whole design (PS and PL) considering that Processing System is an ARM processor with GPIOs and DMA as and interface between the PL and PS.

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In reply to Abuassal:

Yes of Course you can do that. There are no limitations.