I am seeing Illegal combination of drivers for the following code:
output logic [1:0] sig1;
logic [1:0] sig2;
generate
for(genvar i = 0 ; i < 2 ; i++) begin
assign sig1[i] = sig2[i]; //(sig2 is coming from some module instantiation)
end
endgenerate
However when I tried the similar code on EDA playground it works. Can someone help we this?
I guess its a Runtime error, I just gave an example similar to my code.
The error says
Error-[ICSD] Illegal combination of drivers
The variable is declared at filename: linenum1
The first driver is at filename: linenum2
assign sig1[1] = sig2[1];
The second driver is at filename: linenum2
assign sig1[0] = sig2[0];