Variable "x" is driven by multiple structural drivers

SystemVerilog
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3

In reply to cgales:

Hi,

I guess its a Runtime error, I just gave an example similar to my code.

The error says


Error-[ICSD] Illegal combination of drivers
The variable is declared at filename: linenum1
The first driver is at filename: linenum2
  assign sig1[1] = sig2[1];
The second driver is at filename: linenum2
  assign sig1[0] = sig2[0];