Variable and fucntion/task defined in one package but import in mutiple files, the variable and function/task is same object in the mutile different place?

SystemVerilog
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as the title says, if we define a variable and fucntion/task in one package, then we import them in mutiple files, i wonder the variable and function/task is the same object?
for example,in the uvm_pkg, the global task run_test is defined in <uvm_global.svh>, so when we import uvm_pkg::* in different file,can we call the run_test in the multiple different place? if we can, then the run_test called in differenct place is the same one task or different copy?
and how when it come to the variable?

In addition, i already now the situation when class define in one package and import in different place from Dave’s blog: SystemVerilog Coding Guidelines: Package import versus `include.

Thanks for explanation!

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In reply to Yesire-Lincoln:

Importing anything from a package does not create new copies of that. It is only providing visibility to the names in the package without having to provide the fully explicit pathname.

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In reply to dave_59:

I get it, Thanks very much， Dave！
I have do an experiment, so it is!