$value$plusargs not setting the desired value

SystemVerilog
, , ,
6

In reply to puttasatish:

This is not a good solution, because if the order of the enumerations change, it is difficult to adapt to these changes.

Just use the enumerations as they are:


// Example compiled by Putta Satish
 
// Command line options can be as shown below.
 
// +end_type=DELAY +data_type=INCR +mode=SLOW

`include "uvm_macros.svh"
import uvm_pkg::*;

typedef enum { EOT, DELAY} end_type;
typedef enum { RANDOM, INCR, LOAD} data_type;
typedef enum { FAST, SLOW} mode;

class my_config extends uvm_object;
 
  end_type e_t;
  data_type d_t;
  mode m_e;
  
  `uvm_object_utils(my_config);
 
  function new(string name = "config_db");
    super.new(name);
  endfunction
endclass

class drv extends uvm_driver #(uvm_sequence_item);
  my_config cfg_h;

  `uvm_component_utils(drv);
  
  function new(string name = "drv", uvm_component parent = null);
    super.new(name, parent);
  endfunction
 
  function void build_phase(uvm_phase phase);
    if(!uvm_config_db#(my_config)::get(this, "", "STR", cfg_h))
      `uvm_fatal(get_type_name,"getting failed");
  endfunction
 
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    `uvm_info(get_name(), $sformatf("end_type = %s", cfg_h.e_t.name()), UVM_MEDIUM);
    `uvm_info(get_name(), $sformatf("data_type = %s", cfg_h.d_t.name()), UVM_MEDIUM);
    `uvm_info(get_name(), $sformatf("mode = %s", cfg_h.m_e.name()), UVM_MEDIUM);
    `uvm_info(get_name(), $sformatf("Current simulation time is %0t", $time), UVM_MEDIUM);
    phase.drop_objection(this);
  endtask	
endclass		

module top;
  my_config cfg_h_top;
  string str_;
 
  initial
    begin
      cfg_h_top = my_config::type_id::create("cfg_h_top");

      if ($value$plusargs("end_type=%s", str_)) begin
        if (str_ == "EOT") cfg_h_top.e_t = EOT; 
        if (str_ == "DELAY") cfg_h_top.e_t = DELAY; 
      end
      else begin
        `uvm_info("TOP", $sformatf("Using default END_TYPE value"), UVM_MEDIUM);
        cfg_h_top.e_t = EOT;
      end

      if ($value$plusargs("data_type=%s", str_)) begin
        if (str_ == "RANDOM") cfg_h_top.d_t = RANDOM; 
        if (str_ == "INCR") cfg_h_top.d_t = INCR; 
        if (str_ == "LOAD") cfg_h_top.d_t = LOAD; 
      end
      else begin
        `uvm_info("TOP", $sformatf("Using default DATA_TYPE value"), UVM_MEDIUM);
        cfg_h_top.d_t = RANDOM;
      end
      
      if ($value$plusargs("mode=%s", str_)) begin
        if (str_ == "FAST") cfg_h_top.m_e = FAST; 
        if (str_ == "SLOW") cfg_h_top.m_e = SLOW; 
      end
      else begin
        `uvm_info("TOP", $sformatf("Using default MODE value"), UVM_MEDIUM);
        cfg_h_top.m_e = FAST;
      end

      uvm_config_db#(my_config)::set(null, "", "STR", cfg_h_top);

      run_test("drv");
    end
endmodule