UVM reset

UVM
,
1

Hello!

For example I have a DUT with a FSM. FSM has states and from every state if rst_n is low my FSM will go to the IDLE state.
If you look at code coverage in QUESTAsim you can see fsm transition coverege metrics, which covers transitions from state to state.
I need 100% value of this metrics. I understand that I need reset my module during main test, but how to do this in my testbench?
I think about reset driver and reset sequence which will work in parallel with main sequence but may be anybody can give me another good advice how to implement this?

2

In reply to IvanGrafskiy:
The question is how many functional interfaces and agents you have and which agent can aassert the reset signal. Could you please elaborate some more details.

3

I am a novice in verification.
And I write uvm testbench first time.
But I get this problem in simple case - writing testbench for multiplier 35 by 35.
There is one interface for input data with strobe signal and one interface for ouput result with strobe signal. With clock and reset interfaces.
But I think that the problem of reaching 100% transition coverage is for all modules with FSM and I need advices for common case.

4

In reply to IvanGrafskiy:

I guess you will not write a testbench for a multiplier which works only for date = 35.
In your case you have simply 1 interface. An interface is a set of signals/variables which are belonging together. The signals might be data_in, reset, clk, data_out …

5

multiplier 35 bit value mult on 35 bit value

6

In reply to IvanGrafskiy:

OK, I understand. But what is your FSM? This is a simple operation what you are doing.
Your interface might be something like this:
interface mult_if;
bit clk;
bit reset;
logic [34:0] op1;
logic [34:0] op2;
logic [64:0] result;
endinterface

7

In reply to chr_sue:
DSP slice in fpga has only 18 bits wide operands.
And I need to multiply lowest part first, then highest, then add and so on.

8

In reply to IvanGrafskiy:

Your first idea sounds fine (i.e. a reset agent that receives reset sequence_items from a reset sequence).

This is not UVM related, but I don’t recall seeing code coverage for transitions from every state to the RESET state (I’m not an expert on this). May I ask how you coded the FSM in Verilog/VHDL? If I have (hypothetically) a 7-bit FSM with a single reset condition coded in only one place (i.e. the ‘if’ condition), I’m surprised that someone would have to collect coverage on 127 transitions to the RESET state.

if( ~reset_n ) current_state <= IDLE;
else
   case(current_state)
       0:  ....
       1:  ....
      ...
      127: ....
   endcase
9

I find second solution - phase jump.
And it seems more cool then first solution