I am a novice in verification.
And I write uvm testbench first time.
But I get this problem in simple case - writing testbench for multiplier 35 by 35.
There is one interface for input data with strobe signal and one interface for ouput result with strobe signal. With clock and reset interfaces.
But I think that the problem of reaching 100% transition coverage is for all modules with FSM and I need advices for common case.