UVM Register Layer backdoor access peek and poke and VHDL DUT

UVM
1

Is it possible to scope into a VHDL dut through the backdoor?

If so do I use . or / path separators. Also can I scope to a record in the DUT ie top.dut.record[0].data?

I am hoping use signal spy is not the answer :)

Thanks!

2

yes this is possible. Make sure the vhdl is compiled with the correct flags and you can set:

add_hdl_path("tb_top.dut_wrapper.dut.inst_registers.inst_irtws_reg_block");
3

In reply to Phill_Ferg:

Thx Phill.

I am a questa user…you were referring to +acc for compile options?

4

In reply to nsshah:

No the +acc arguments relate to optmisation of compiled modules.

Although i don’t think you need this but to be on the safe side i added “-misxedsvvh” to all of my vcom commands

5

In reply to Phill_Ferg:

Heres an update and a resolution. The backdoor worked seamlessly with easy signals. But questa cannot handle VHDL array of records. I was able to scope to top.dut.record(0) but not top.dut.record(0).data. It does not like in some cases. Also without scoping the fields inside the record, the backdoor is worthless.

Thanks for your help Phill. I have the FAE looking into this with an example. They are willing to patch questa with a fix (and I suspect it will get rolled in at some point).

6

In reply to nsshah:

Good spot!

I used the mentor register generator with our DUT so we don’t fall into that trap. For the amount of register in the DUT the time spent creating the register model outweighed the risk in used the register generator.
Perhaps you could try that as a in interim solution?

Good luck!

7

In reply to Phill_Ferg:

Are you using HDL designer? I am using the freebie uvm reg assistant bundled in questa. The department i am in auto generates the registers and interface code…we are trying to migrate to ipxact for both to get a 1 click solution.

I think mentor should be able to fix it quick. they have access to our database so already have the example. Worst case I can path to where the record gets used.

8

In reply to nsshah:

I though the register generator parses IPXACT? I can use either the HDL or questasim version, although i can’t remember the questa limitations.
From the registers we generate i haven’t seen records used in the VHDL register block.

If your registers are generated from a separate source i understand now

9

In reply to Phill_Ferg:

Your company has the ‘full up’ version which is using an HDL designer license. We are planning on using that to get the IPXACT definition to make our ‘separate source’ and the ral package. Right now I am using the excel macro spreadsheet they give you and entering stuff in there. If you look in the questa install, its RUVM folder.

I’ll keep this thread updated with mentors record fix. Really appreciate your help.