In reply to dolovk:
The UVM approach in general is you cannot modify your environment on the fly, i.e. in the run_phase. Each test can configure the environment for certain test requirements. But this happens prior to starting the simulation. Even it woulkd be possible to modify your environment on the fly you ahd a standalone, non-reusable environment. It would work for your specific application but you could not reuse it.
I believe it is worth to clean-up your register models, at least for your toplevel testbench. I know this will cost some effort, but it results in a clean and reusable environment.