In reply to chr_sue:
Yes, I agree with that. It should be like that. But this is very particular case in which I am facing the problem where I have thousands of registers already, 9 testbenches, various interfaces and the register environment is particularly made, non-standard. Various registers width and non-aligned addresses. I need to develop UVM RAL for all these registers, to translate the old way of registers (API…) into the standard ones, according to the UVM.
Designer created on this way several years ago in order to reduce space and to have one access at the time for several registers, among other advantages and needs.
I would like to understand can this project be realized at all. If so, the idea that I have now is to make “user-defined write()” using callbacks, pre_write(), post_write(), in order to manipulate with number of bits, accesses and addresses. I must override the automatic RAL behavior, adjusting workaround.
Is it possible to have information about the register’s width and address in callback pre_write() at the moment when we call write() for the certain register?
If I would know the reg width and the parity of that address, I could calculate and set the exact number of access and the right address (for that uvm_reg_item rw).
It is similar with the sequences when we have start_item and item_done, calling write() is the same. Now I want with calling only once write() to actually have several times “start_item - item_done” by incrementing the addresses.