In reply to dolovk:
I believe you have to adopt your interpretation of your registers to the UVM RL approach and this is based on a fixed register width.
I’m always assuming a storage place which has a specific address as 1 register, resulting in 3 registers with a width of 8 bits. You can access only 1 regsiter at the same time. If you need the data from the 3 registers in a series you can do this by accessing your registers in the defined order.