UVM RAL access type

UVM
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3

In reply to chr_sue:

In reply to UVM_SV_101:
Could you please explain wher these terms come from?
I guess you mean the access of the registers in the DUT (HW) and in the register morror of the testbench (SW).
In my understand this terminology is misleading.

For translating from RDL to RAL
RDL :

field {
        name = "CNTR";
        fieldwidth = 1;
        hw = w;
        sw = rw;
       }CNTR[2:2] = 0;

This reg field would translate to following in RAL:


this.CNTR =uvm_reg_field::type_id::create("CNTR",,get_full_name());
this.CNTR.configure(this, 1, 2, "RW", 1, 1'h0 ,1,0,0);

My question is access policy from RDL “sw = rw” translated to “RW” in RAL.

  1. What does “hw” and “sw” mean in RDL
  2. In RDL if the access type for “hw and sw” is different, why does RAL picks “sw” access policy?