A basic introduction to phasing is described in the cookbook, as will as in the short course on Basic UVM. Essentially, a test is broken up into an ordered set of steps. And because a testbench is broken up into a set of many concurrently executing components, the UVM base class libraries coordinate the execution of those step so that all components complete step1 before moving on to step_2_. It would be very difficult to connect one component to another component if that component does not exist yet.
If you are familiar with gate or RTL simulation, you are used to the compiler elaborating all components and their connections for you. But since the testbench is dynamically constructed, the UVM does this for you at run time 0.
Also, we do not recommend calling super.build_phase() unless you are using the UVM field macros, which we also do not recommend because of the poor performance they introduce.